Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
An overshoot pulse current may be added to a signal. For example, in a writer pre-amplifier design, a writer output signal is used to signal when to write to a disk for a disk drive. FIG. 1 depicts an example of a writer output signal 102. A writer output signal 102 includes a direct current (DC) writer current signal 104 that is combined with an overshoot pulse current signal 106. Overshoot pulse current signal 106 is generated using toggled pulse signals. The result of combining the two signals is writer output signal 102.
FIG. 2A depicts an example of a circuit 200 that is used to generate overshoot pulse current signal 106 and FIG. 2B depicts waveforms for circuit 200. Circuit 200 uses an inverter chain 202 to create a delay and generates pulse signals from an input clock (CLK). The output of a logic element 204 (e.g. an AND gate) is overshoot pulse current signal (BSTL) 106. Advantages of using inverter chain 202 to generate the pulse signals include simplicity, good signal integrity, and low power.
And gate 204 receives clock signal CLK and an inverted delayed clock signal CLKBD and creates overshoot pulse current signal 106. As shown in FIG. 2B, at 206, a rising edge of overshoot pulse current signal 106 is aligned with a rising edge of clock signal CLK. At 208, the falling edge of overshoot pulse current signal 106 is aligned with the falling edge of delayed clock CLKBD. This process continues as pulses are generated. The pulses may be toggled to be positive and negative to create overshoot pulse current signal 106.
In some designs, such as in a pre-amplifier writer design, using an inverter chain to generate pulses may be problematic. For example, a typical pulse width that is required for a pre-amplifier writer is programmable between 150 picoseconds (ps)-500 ps. However, the data rate of a writer current signal 104 exceeds 3 gigabits (gb) per second (ps), which gives a data duration of 333 ps. This results in a possible scenario where the pulse width of overshoot pulse current signal 106 may be selected to be larger than the data duration at a high data rate. For example, the pulse duration may be 400 ps, but the data duration is 333 ps. In this case, referring to FIG. 1, the overshoot pulse current signal 106 will be larger than the pulse of writer current signal 104. In this case, pulse signals will collapse.
FIG. 3 depicts an example when pulse signals collapse and are not aligned with clock signal CLK. When the delay is longer than the data duration, overshoot pulse current signal 106 is not aligned with clock signal CLK. For example, at 302, the value of clock signal CLK is 1 and the value of the inverted delayed clock signal CLKBD is 0, which results in a value of 0 being output by AND gate 204. At 304, the values of clock signal CLK and the inverted delayed clock signal CLKBD are both 1, and AND gate 204 outputs a high signal that results in the rising edge of overshoot pulse current signal 106. Thus, the rising edge of overshoot pulse current 106 is not aligned with clock signal CLK. To rectify the misalignment, techniques using circuits other than an inverter chain are used to generate the delay.